1. Field of the Invention
This invention relates to a phase locked loop including, as principal constituent elements, a phase comparator, charging pump circuit, a low-band filter (which is also referred to as a "low-pass filter"), a voltage controlled oscillator (which is generally abbreviated to "VCO") and a frequency divider, and having a function of causing the frequency of an oscillation output signal to conform to the frequency of an input signal by changing an output voltage in accordance with the phase difference between the input signal and the oscillation output signal from the voltage controlled oscillator (or from the frequency divider), and relates also to a semiconductor device in which the phase locked loop containing the constituent elements described above is formed on one chip and integrated into this chip. Such a phase locked loop is generally referred to as "PLL", and is used for portable telephone sets and so forth.
More particularly, the present invention relates to an improvement in the linearity of the output voltage characteristics of a charging pump circuit portion for generating an analog phase difference output voltage on the basis of a digital phase difference signal representing the phase difference between an input signal outputted from a phase comparator and an oscillation output signal, and for inputting the analog phase difference output voltage into a low-pass filter (Hereinafter, the term "charging pump circuit portion" will be used in the sense that that circuit constitutes a part of the PLL.).
2. Description of the Related Art
First, the construction of a phase locked loop according to the prior art and its operating characteristics will be explained in order to make the problems concerning the conventional phase locked loop more easily understood, with reference to FIGS. 1 to 5.
FIG. 1 is a block circuit diagram showing the construction of the phase locked loop according to the prior art, wherein, however, the construction of the phase locked loop is illustrated in a simplified form so as to simplify the explanation.
As shown in FIG. 1, the phase locked loop 10 generally includes a phase comparator 2, a charging pump circuit portion 30, a low-pass filter 60, a voltage controlled oscillator (VCO) 8 and a frequency divider 9, and these constituent elements constitute a control circuit for a loop system.
In FIG. 1, the phase comparator 2 enables the phases of an input signal Sr and an oscillation output signal Sv to conform to the phase of a reference signal (for example, a clock signal) so as to compare the phase difference between the digital input signal Sr and the oscillation output signal Sv (or a phase locked signal So) of the voltage controlled oscillator 8 (or the frequency divider 9), for example.
After phase alignment is effected in this way, two kinds of phase difference comparison signals outputted from the phase comparator 2 are inputted to a charging pump circuit portion 30. In this charging pump circuit portion 30, a first transistor TR1 comprising a P-channel field effect transistor (P-channel FET), etc., and a second transistor TR2 comprising an N-channel field effect transistor (N-channel FET), etc., are connected with each other, in a push-pull manner, between a positive terminal of a power supply voltage Vd and a negative terminal of a power supply voltage --Vd. The two kinds of phase difference comparison signals described above are inputted to the gates of the first and second transistors TR1 and TR2, respectively, and are outputted as a phase difference output voltage from the junction of these transistors TR1 and TR2.
Further, the phase difference output voltage from the charging pump circuit portion 30 is inputted to a low-pass filter 60 which is also referred to as a "loop filter". This low-pass filter 60 constitutes an integration circuit including two resistors R1 and R2 and one capacitor C1, and has a function of smoothing the phase difference output voltage from the charging pump circuit portion 30.
The output voltage smoothed by the low-pass filter 60 has a voltage value corresponding to the phase difference. Therefore, when the smoothed output voltage is inputted to the voltage controlled oscillator 8 through a capacitor 65 provided for noise elimination, etc., an oscillation output signal Sv having an oscillation frequency corresponding to the phase difference is outputted from the voltage controlled oscillator 8. This oscillation output signal Sv is inputted, either directly to the phase comparator, or is inputted to the phase comparator 2 after the oscillation frequency is suitably regulated through the frequency divider 9. In other words, in the case of this example, the charging pump circuit portion 30 and the voltage controlled oscillator 8 operate so as to cause the oscillation frequency of the oscillation output signal Sv to conform to the frequency of the input signal Sr in accordance with the phase difference and in this way, the phase of the phase locked signal So as the final output of the phase locked loop 10 is locked.
In the phase locked loop 10 including the charging pump circuit portion 30 as shown in FIG. 1, the phase locked loop can be constituted by a simple circuit construction by utilizing a simple switch operation of the transistors, etc., inside the charging pump circuit portion. According to the phase locked loop of this kind, an output voltage having good linearity can be generated by the low-pass filter 60, ideally within the range of the phase difference of from +.pi. radian (rad) to -.pi. radian (including both of the leading phase and the lagging phase).
In the phase locked loop 10, however, a stray capacity Cs usually exists at the circuit portions disposed at the back of the output terminal of the charging pump circuit portion 30, e.g., in a portion of a wiring pattern. Therefore, ideal output voltage characteristics cannot be obtained in which the phase difference is in the proximity of 0 radian, owing to an influence of this stray capacity Cs. In consequence, the phase locked loop 10 has greatly different output voltage characteristics between the above portions in which the phase difference is in the proximity of 0 radian and portions having other phase differences. Particularly when the resistance values of the two resistors R1 and R2 in the low-pass filter 60 increase (up to values not smaller than 100 kilo-ohms (k.OMEGA.), for example) and an impedance of the low-pass filter 60 increases, the influence of the stray capacity Cs becomes larger, and the output voltage characteristics near the phase difference of 0 (zero) radian (that is, the phase lock characteristics) tend to become remarkably different from characteristics obtained by theoretical calculations. As a result, the phase lock characteristics of the phase locked loop 10 become unstable.
As described above, in the phase locked loop according to the prior art, a charge is accumulated in the stray capacity Cs existing at the circuit portions after the output terminal of the charging pump circuit portion 30 near the phase difference of 0 radian, and even when the charging pump circuit portion 30 stops outputting a voltage, electric charges accumulated in the stray capacity Cs flow into the low-pass filter 60. The state in which the charges flow into the low-pass filter 60 is inverted between the leading phase and the lagging phase, so that an extremely large change of the output level occurs near the phase difference of 0 radian. The mode of the change of the phase difference output voltage of the charging pump circuit portion 30, corresponding to the output voltage of the low-pass filter 60 near the phase difference of 0 radian, will be further explained with reference to FIGS. 2 to 5.
FIG. 2 is a timing chart useful for explaining an operation of the charging pump circuit portion according to the prior art near the phase difference of 0 radian and in the leading phase; FIG. 3 is a timing chart useful for explaining an operation of the charging pump circuit portion according to the prior art near the phase difference of 0 radian and in the lagging phase; and FIG. 4 is a timing chart useful for explaining an operation of the charging pump circuit portion according to the prior art almost exactly at the phase difference of 0 radian.
FIG. 2 shows the case where the phase difference between a digital input signal Sr ("L" (Low) level or "H" (High) level) and the oscillation output signal Sv is approximately zero (0 radian) and the phase of the oscillation output signal Sv is slightly ahead of the phase of the input signal Sr (the case of the leading phase).
In this case, the second transistor TR2 is turned ON (conductive state) for each period corresponding to the phase difference generated due to the difference between times of leading edges from the "L" level to the "H" level of the input signal Sr and the oscillation output signal Sv, and a negative phase difference output voltage is outputted from the charging pump circuit portion 30. Both the first and second transistors TR1 and TR2 are turned OFF (non-conductive state) for other periods, and the phase difference output voltage from the charging pump circuit portion 30 should become 0 (zero). However, as described above, after the phase difference output voltage from the charging pump circuit portion 30 changes to 0, the electric charges accumulated in the stray capacity Cs flow into the lowpass filter 60 in the portion in which the phase difference is in the proximity of 0. Since these charges flowing into the low-pass filter 60 are discharged through the resistors inside the low-pass filter 60, the time required before the negative phase difference output signal returns to 0 becomes relatively long.
FIG. 3 shows the case in which the phase difference between the digital input signal Sr and the oscillation output signal Sv is approximately 0 and the phase of the oscillation output signal Sv is slightly behind the phase of the input signal Sr (in the case of the lagging phase).
In this case, the first transistor TR1 is turned ON for each period corresponding to the phase difference generated due to the difference between times of leading edges from the "L" level to the "H" level of the input signal Sr and the oscillation output signal Sv, and a positive phase difference output voltage is outputted from the charging pump circuit portion 30. Both the first and second transistors TR1 and TR2 are turned OFF for other periods, and the phase difference output voltage from the charging pump circuit portion 30 should become 0. However, in this case too, the charges flowing into the low-pass filter 60 are discharged through the resistors inside the low-pass filter 60, so that the time required before the positive phase difference output voltage returns to 0 becomes relatively long.
FIG. 4 shows the case in which the phase difference between the digital input signal Sr and the oscillation output signal Sv is almost exactly 0 and the phase is only slightly the lagging phase or only slightly the leading phase.
In this case, the phase difference generated due to the difference between times of leading edges from the "L" level to the "H" level of the input signal Sv and the oscillation output signal Sv is substantially 0. Therefore, both the first and second transistors TR1 and TR2 are turned OFF for all the periods, and the phase difference output voltage from the charging pump circuit portion 30 should remain at 0. However, in this case, too, the charges accumulated in the stray capacity Cs during only the slight period of the lagging phase or the leading phase flow into the low-pass filter 60 and are discharged through the resistors inside the low-pass filter 60. In consequence, in both of the cases in which the phase is only slightly the lagging phase and in which it is only slightly the leading phase as shown in FIG. 4, a positive pulse-like voltage and a negative pulse-like voltage are generated, respectively.
Since the polarity of the charges accumulated in the stray capacity Cs is inverted between the leading phase and the lagging phase, an extremely large change of the output level occurs on the output side of the charging pump circuit portion 30 in the portion where the phase difference is in the proximity of 0 radian. As a result, the output voltage smoothed by the low-pass filter 60 abruptly changes near the phase difference of 0 radian as represented by the graph of FIG. 5. In other words, linearity in the phase locked loop with respect to the change of the phase difference is impeded by an influence of the stray capacity Cs near the phase difference of 0 radian.
In the explanation given above, the case in which the phase difference output voltage is 0, when the phase difference is 0, is used as the reference case. However, it should be noted that the explanation can be given exactly in the same way by setting a reference voltage to an arbitrary voltage and by regarding the difference between this arbitrary voltage and the phase difference output voltage as the output of the phase comparator 2 even though the phase difference output voltage is the above arbitrary voltage when the phase difference is 0.
Generally, the response characteristics of a phase locked loop are calculated on the basis of a theoretical circuit having ideal constants. Further, a design of the phase locked loop is carried out on the basis of results obtained by calculations using the theoretical circuit. However, because the output voltage of the phase locked loop abruptly changes near the phase difference of 0 owing to the influence of the stray capacity Cs as described above, the constants of the theoretical circuit change, too. For this reason, the response characteristics obtained by the calculations using the theoretical circuit do not coincide with the practical response characteristics, and the phase locked loop must be designed on the basis of troublesome trial-and-error experiments.